1. Field of the Invention
The present invention relates to an electrically erasable programmable non-volatile semiconductor memory (called "EEPROM" in the specification) and a method for driving the EEPROM. More specifically, the present invention relates to a flash type EEPROM in which all contents of the EEPROM can be simultaneously erased, and a method for driving the flash type EEPROM.
2. Description of Related Art
In general, flash type EEPROMs have an erase mode, a write mode and a read mode. In the erase mode, all memory cells are simultaneously erased. However, the memory cells in the EEPROM have dispersion in a gate length and in a gate oxide thickness, and consequently, dispersion in a memory cell erasing speed. In other words, the flash type EEPROM has a substantial difference in the erasing speed between a memory cell having the fastest erasing speed and another memory cell having the slowest erasing speed. On the other hand, an erasing time t.sub.PE is determined by a pulse width of an erasing signal. Therefore, this pulse width of the erasing signal is set to fulfil the following conditions:
(1) In the erased condition, the memory cell having the fastest erasing speed has a threshold voltage higher than 0 V, and PA0 (2) In the erased condition, the memory cell having the slowest erasing speed has a threshold voltage lower than 3 V.
The reason for the condition (1) is that: if the erased memory cell has the threshold voltage lower than 0 V (this condition is called a "excess erase"), the excess erased memory cell is turned on in the read mode without exception even if it is not selected. Therefore, it becomes impossible to read the memory cells.
On the other hand, the reason for the condition (2) is that: a standard range of the voltage supply voltage Vcc for the flash type EEPROM in the operating condition is ordinarily 5 V.+-.0.5 V. Therefore, in order to obtain a cell current Ion required for stably reading the erase memory cell, it is necessary to fulfil a condition of V.sub.TM (E).ltoreq.3 V.
Therefore, the erasing time is set to ensure that the dispersion ofthe threshold in all the erased memory cells is required to be in the range of greater than 0 V but less than 3 V. If the erasing time is too short, the threshold of the erased memory cell does not becomes less than 3 V. If the erasing time is too long, the threshold of some erased memory cell would become less than 0 V.
Thus, an erase verify mode has been provided in the flash type EEPROM in order to set the erasing time optimized to the memory cells. After the erasing has been completed, the EEPROM is put in the erase verify mode, and all the memory cells are sequentially read out in order to check whether or not each of the memory cell fulfils the above mentioned condition (1).
For this purpose, the conventional flash type EEPROM has included a circuit for generating an erase verify voltage such as 3 V, and a voltage switching circuit having a pump-up circuit for supplying a pumped-up voltage in the writing mode and in the erase mode, the voltage supply voltage in the read mode and the erase verify voltage in the erase verify mode. For the purpose of generating the erase verify voltage, the erase verify voltage generating circuit is connected to receive a reference voltage supplied from a reference voltage generating circuit. For example, this reference voltage generating circuit is composed of one P-channel enhancement MOS transistor and first, second and third N-channel enhancement MOS transistors connected in series, each of the MOS transistors being connected in the form of active load in which a gate and a drain of each N-channel enhancement MOS transistor are short-circuited, and a gate of the P-channel enhancement MOS transistor is grounded. A source of the P-channel enhandcement MOS transistor is connected to a voltage supply voltage, and a drain of the P-channel enhancement MOS transistor is connected to a drain of the first N-channel enhancement MOS transistor. A source of the third N-channel enhancement MOS transistor is grounded. A connection node between the drain of the P-channel enhancement MOS transistor and the drain of the first N-channel enhancement MOS transistor gives the reference voltage Vref. Therefore, assuming that all the N-channel enhancement MOS transistors have the same threshold V.sub.TN, the reference voltage Vref is given by 3.multidot.V.sub.TN. Namely, if each of the three N-channel enhancement MOS transistor has the threshold V.sub.TN of 1 V, the reference voltage of 3 V is given. On the basis of this reference voltage, the erase verify voltage having a large current capacity is generated.
In order to precisely verify the threshold of the erased memory cell, the erase verify voltage and hence the reference voltage are required to be stable against variations of process parameters, fluctuation of the voltage supply voltage and a temperature variation.
However, the above mentioned reference voltage generating circuit is disadvantageous in that if the threshold V.sub.TN varies by .DELTA.V.sub.TN, the reference voltage Vref inevitably varies by 3.multidot..DELTA.V.sub.TN. For example, if the threshold V.sub.TN varies from 1.0 V to 1.2 V due to variation of process parameters, the reference voltage Vref varies from 3.0 V to 3.6 V. In this case, if one memory cell has the threshold of 3.5 V after completion of the erasing operation, when the memory cell having the threshold of 3.5 V is verified in the erase verify mode, it is discriminated that the erase of the memory cell having the threshold of 3.5 V has duly been completed. Therefore, when the memory cell having the threshold of 3.5 V is read in the reading mode, the cell current I.sub.ON of the memory cell having the threshold of 3.5 V is lower than a designed value, and therefore, a reading speed becomes slow.
When the threshold voltage V.sub.TN is lowered due to a drop of the temperature, a similar disadvantage is encountered.
As mentioned above, in the conventional flash type EEPROM, since the erase verify voltage is determined by the output voltage of the reference voltage generating circuit provided in the same chip, it is difficult to generate the erase verify voltage stable against variations of process parameters, fluctuation of the voltage supply voltage and a temperature variation. Therefore, the erase verify voltage has inevitably varied due to the variations of process parameters, the fluctuation of the voltage supply voltage and the temperature variation. As a result, it has not been possible to precisely detect whether or not the threshold voltage V.sub.TN of the erased memory cell is less than a desired erase verify voltage V.sub.EV.
In order to obtain the erase verify voltage stable against variations of process parameters, fluctuation of the voltage supply voltage and a temperature variation, the prior art has no way other than (1) to make the reference voltage generating circuit complicated or large in the circuit scale, or to use bipolar transistors which inevitably make the manufacturing process complicated.